(a) Field of the Invention
The present invention relates to a multilayer wiring board, more specifically, to a multilayer wiring board adapted for an effective drawing out (fan out) of wiring patterns for each wiring layer.
(b) Description of the Related Art
In recent semiconductor devices, the functionality and density of logic devices have been enhanced, and the number of input-outputs has increased. Accordingly, products have been provided in which a shortage of an electrode formation space due to an increase in the number of the input-outputs is compensated by placing a large number of electrodes on an electrode formation surface of a semiconductor element (chip). For example, in a type of products in which a semiconductor chip is mounted on a wiring board by flip-chip bonding, where electrodes are arranged only in a peripheral portion of an electrode formation surface of the semiconductor chip, just the provision of one layer of wiring patterns in the wiring board makes it possible to connect all the electrodes to the wiring patterns. Namely, a wiring pattern can be drawn out from a pad formed at a position on the wiring board which corresponds to each electrode of the chip. However, where a large number of electrodes are arranged in a grid or an area array pattern on the electrode formation surface of the semiconductor chip, there may occur a disadvantage in that wiring patterns cannot be drawn out from all of pads in one wiring layer, although occurrence of the disadvantage depends on the number of pads and the arrangement pitch of pads formed on the wiring board.
As a method of eliminating such a disadvantage, there is the following method: a wiring board on which a semiconductor chip is to be mounted is formed to be multilayered, and all of electrodes of the semiconductor chip are respectively connected to wiring patterns by appropriately placing the wiring patterns in wiring layers stacked. One example thereof is shown in FIG. 4. In the constitution shown in FIG. 4, a semiconductor chip 5 in which a large number of electrodes 6 are arranged in a grid pattern on a mount surface is mounted on a multilayer wiring board 1 in which wiring layers are stacked in four layers. Using this multilayer wiring board 1, all of the electrodes 6 of the semiconductor chip 5 can be electrically connected to wiring patterns 2, and to wiring patterns 2a in internal layers through via holes 3, and further to external connection terminals 4 through via holes 3.
When the semiconductor chip is mounted on the wiring board as described above, in case of the number of electrodes being not large, a multilayer wiring board having four layers such as shown in FIG. 4 is enough. However, for example, where a semiconductor chip with 30×30 pins, 40×40 pins, or the like, in which an extremely large number of electrodes are arranged, is mounted, the number of wiring layers needs to be further increased because the number of rows for which a fan out (drawing out of wiring patterns) can be performed from each wiring layer is limited. In this case, in order to constitute a multilayer wiring board by stacking wiring layers each of which has wiring patterns formed at high density, a high-density wiring method such as a build-up method is employed.
FIG. 5 schematically shows the constitution of a multilayer wiring board according to one example of the prior art, which is constituted using a build-up method, and shows a partial cross-sectional structure thereof. In the illustrated multilayer wiring board (build-up printed circuit board) 20, four wiring layers 22 are stacked on each of the top and bottom of a core substrate 21 with interlayer insulating layers 23 interposed therebetween. For convenience, each of the wiring layers 22 is referred to as a wiring layer of a “first layer,” that of a “second layer,”. . . , and that of an “eighth layer,” respectively, from the top. Each wiring layer 22 includes a plurality of pads P placed in a predetermined arrangement, and a plurality of wiring patterns WP each of which is formed in such a manner that one end thereof is connected to any one of the plurality of pads P and that the other end thereof is drawn outward (left side in the illustrated example). It is noted that, among the pads P included in the wiring layers 22, there are also pads P to which wiring patterns WP are not connected. Further, vertically adjacent wiring layers 22 (pads P) are electrically connected to each other through via holes VH (conductors filled therein) formed in the interlayer insulating layer 23. Incidentally, a semiconductor chip is mounted by flip-chip bonding on the pads P provided in the wiring layer 22 of the first layer, as indicated by dashed lines in the drawing.
FIGS. 6A and 6B schematically show the arrangement of pads and the drawing-out of wiring patterns in (portion of) the wiring layers of the first and second layers partially constituting the above-described multilayer wiring board 20. The arrangement of the pads P1 and P2 provided in the wiring layer 22 of the first layer coincides with the arrangement of electrodes arranged in a grid pattern on a mount surface of a semiconductor chip to be mounted on the multilayer wiring board 20. Further, for the pads P1 and P2 from which wiring patterns WP have been drawn out in the wiring layer of the first layer (FIG. 6A), there is no need to place corresponding pads in the wiring layer of the second layer (FIG. 6B). Accordingly, pads to be provided in the second layer correspond to the pads from which wiring patterns WP are not drawn out in the first layer, and both of these pads are electrically connected to each other through the via holes VH (FIG. 5).
As shown in FIGS. 6A and 6B, in a known method of drawing out wiring patterns WP, the wiring patterns WP are drawn out in groups of two rows each in order from outer portions of rectangular regions PR1 and PR2 (hereinafter also referred to as “pad placement regions”) in which the pads are placed. In this case, for the pads P2 located in internal portions (second row from the outside) of the pad placement regions PR1 and PR2, wiring patterns WP are passed through the spaces between adjacent pads P1 in the outermost portion to be linearly drawn out to the respective outsides of the pad placement regions PR1 and PR2 as shown in the drawing. Thus, in each of the arrangements of the wiring patterns WP on the outsides of the pad placement regions PR1 and PR2, the wiring patterns WP drawn out from the pads P1 placed in the outermost portion of the relevant pad placement region and the wiring patterns WP drawn out from the pads P2 in an internal portion of the relevant pad placement region are alternately placed.
Technologies relating to the above-described prior art include, for example, as described in Japanese unexamined Patent Publication (JPP) 11-297885, a multilayer circuit board in which circuit boards are stacked. In this multilayer circuit board, for the circuit board of a first layer on which an electronic component is to be mounted, circuit patterns are drawn out from all of lands placed in the outermost portion of a region in which lands are arranged, from lands placed on a diagonal line of the region, and from lands placed in a vicinity of the diagonal line; and, for each of the circuit boards of the second and subsequent layers, circuit patterns are drawn out from all of lands placed in an outermost portion of a region in which lands are arranged, and lands placed in a peripheral portion of a vacant space which is formed in the direction of the diagonal line by drawing out the circuit patterns in the upper layers.
As described above, in the prior art, where a semiconductor chip with 30×30 pins, 40×40 pins, or the like, in which an extremely large number of electrodes are arranged, is mounted on a wiring board, the number of wiring layers tends to increase because the number of rows for which a fan out (drawing out of wiring patterns) can be performed from each wiring layer is limited.
However, the increase in the number of wiring layers has serious problems of product yield, reliability, and cost. Namely, where a wiring board is formed to be multilayered, wiring patterns are formed in each layer, and the wiring patterns are electrically connected to each other between layers through via holes, thus sequentially stacking the layers. Accordingly, extremely high precision is required for a manufacturing process thereof, and the product reliability is not necessarily, high even at present. Further, the case of multilayer stacking involves technical difficulty because the nonexistence of defects in all layers is required. Accordingly, a reduction in the number of wiring layers is effective for manufacturing a multilayer wiring board with high yield.
Moreover, when a drawing out (fan out) of wiring patterns is performed for each wiring layer, there may occur a disadvantage in that lower wiring layers cannot be reached where wiring patterns are drawn out in order from the upper wiring layer (i.e., wiring patterns must be drawn out in an intermediate wiring layer, and connections to the underlying wiring layer cannot be established by means of via holes or through holes).
For example, in the case of a multilayer wiring board by a build-up method such as shown in FIGS. 5, 6A, and 6B, wiring patterns are drawn out in groups of two rows each in order from an outer portion of the pad placement region PR1 or PR2 in each of the first and second layers. Accordingly, when this drawing-out method is applied to the third layer, a disadvantage occurs as shown in FIGS. 7A and 7B. Namely, the pads P1 provided in the third layer correspond to the five pads from which wiring patterns WP are not drawn out in the second layer (FIG. 6B), and the third and second layers can be electrically connected to each other through the via holes VH (FIG. 5) formed on the five pads P1. However, the third layer and the underlying layers (in the example shown in FIG. 5, the fourth and fifth layers on the core substrate 21) cannot be connected to each other, because the regions of through holes TH (FIG. 7A) to be formed in the core substrate 21 overlap each other and the through holes cannot be arranged in terms of space. Accordingly, wiring patterns WP must be fanned out in the third layer as shown in FIG. 7B. As a result, there has been a disadvantage in that the wiring layers 22 of the fourth and subsequent layers of the build-up printed circuit board 20 (FIG. 5) are not effectively used.
In order to cope with such a disadvantage, it is conceived that the diameter of the through holes TH to be formed in the core substrate 21 is reduced. However, since such through holes are often formed by drilling, the diameter of the through holes is apt to increase under present circumference (approximately 250 to 300 μm in the state if the art). Accordingly, this is not an effective method because of technical limitations in reducing the diameter of the through holes. Further, as the causes of the above-described disadvantage, factors such as the line width of wiring patterns passed through the spaces between adjacent pads are recurred in addition to the size of the through holes. However, there are similarly technical limitations in reducing the line width of the wiring patterns.